Discrete devices including EAPROM transistor and NVRAM memory cell with edge defined ferroelectric capacitance, methods for operating same, and apparatuses including same

ABSTRACT

A memory cell includes a charge amplifier having a gate adjacent to a channel region coupling source and drain regions, a digitline coupled to one of the source and drain regions, a ground lead coupled to the other of the source and drain regions, a ferroelectric capacitor coupled to the gate, and a wordline coupled to the ferroelectric capacitor. Advantageously, the charge amplifier can be a CMOS transistor. Preferably, the gate is coupled to the ferroelectric capacitor by polysilicon, the junction formed at the gate has an intrinsic capacitance, and the capacitance of the ferroelectric capacitor is based on the magnitude of the intrinsic capacitance. Alternatively, the gate is coupled to the ferroelectric capacitor by polysilicon, the junction formed at the gate has an intrinsic capacitance, and the physical size of the ferroelectric capacitor is based on the magnitude of the intrinsic capacitance. In this case, the thickness of a ferroelectric material layer in the ferroelectric capacitor can be based on the magnitude of the intrinsic capacitance. A memory cell array, a memory module, and a processor based system can all be fabricated from this memory cell. Methods for reading data out of and writing data into the memory cell are also described.

This is a Continuation-in-Part of U.S. application Ser. No.(09/385,380), which is entitled “DYNAMIC RANDOM ACCESS MEMORY (DRAM)CELLS WITH REPRESSED FERROELECTRIC MEMORY, METHODS OF READING SAME, ANDAPPARATUS INCLUDING SAME”, and which was filed on Aug. 30, 1999, nowU.S. Pat. No. 6,141,238.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to discrete elements such as electricallyalterable programmable read-only memory (EAPROM) and nonvolatile randomaccess memory (NVRAM) devices. More specifically, the present inventionrelates to EAPROM and NVRAM cells where data is stored using aferroelectric capacitor incorporated in the cells. Methods foroperating, writing to and reading from, such DRAM, logic devices, memoryarrays, and systems containing these cells are also disclosed.

2. Description of Related Art

Dynamic random access memories (DRAMs) are the most cost-effective,high-speed memory used with present day computers. DRAMS last nearlyindefinitely. Moreover, DRAMs are available in very high densityconfigurations, e.g., 64 megabytes (MB). However, DRAMS can only storeinformation for a limited time without constant refreshing and lose allknowledge of their state once power is removed.

Ferroelectric capacitors are currently being used as nonvolatile memorydevices, as disclosed in U.S. Pat. No. 4,888,733, which is entitled“Nonvolatile Memory Cell and Sensing Method” and discloses a twotransistor, one capacitor (2T/1C) memory cell. In addition,ferroelectric capacitors are often employed in nonvolatile random accessmemories (NVRAMs). Memory cells having structures approximating that ofDRAMs, i.e., arranged in the conventional one transistor, one capacitor(1T/1C) memory cell pattern, are disclosed in U.S. Pat. Nos. 5,600,587(Ferroelectric Random Access Memory), 5,572,459 (Voltage Reference for aFerroelectric 1T/1C Based Memory), 5,550,770 (Semiconductor MemoryDevice Having FE Capacitor Memory Cells with Reading, Writing, andForced Refreshing Functions and a Method of Operating the Same),5,530,668 (Ferroelectric Memory Sensing Scheme Using Bit LinesPrecharged to a Logic One Voltage), and 5,541,872 (Folded Bit LineFerroelectric Memory Device). It should be mentioned that all of thepatents cited above are incorporated by reference herein for allpurposes.

In the above-mentioned patents, the capacitor in a 1T/1C DRAM structureis replaced by a ferroelectric capacitor, as illustrated in FIG. 1(a).The memory cell 1 of FIG. 1(a) includes a wordline 10, a digitline 12, atransistor 14 and a ferroelectric capacitor 16. In operation, theremnant charges are detected on a bit line in a manner similar to theoperation of a conventional DRAM. However, these structures are notwithout attendant problems.

There is an extensive body of literature on both the electricalcharacteristics of ferroelectric capacitors and applications in cellssimilar to conventional DRAMs, except that these cells are classified asnonvolatile RAMs (NVRAMs) instead of DRAMs. One recent publication by K.Asaril et al., entitled “Multi-Level Technologies for FRAM EmbeddedReconfigurable Hardware” (IEEE Int. Solid-State Circuits Conf., SanFrancisco 1999, pp. 108-109), describes the use of a ferroelectriccapacitor in a ferroelectric RAM (FRAM)which is employed with lowvoltage to store and access RAM data superimposed on less-frequentlyaccessed read-only memory (ROM) data in the same cell. See U.S. Pat. No.5,539,279, entitled “Ferroelectric Memory.” The RAM data is volatile andneeds to be refreshed on a regular basis, or this aspect of the cellacts like a DRAM. The electrically alterable read-only memory (EAROM),e.g., an electrically erasable programmable ROM (EEPROM) data isnonvolatile. In other words, the FRAM acts like a DRAM with a“repressed” nonvolatile read only “memory,” or “repressed memory.”

Other applications use the ferroelectric capacitors as part of a stackedgate structure similar not to DRAMs but rather to EEPROM or flash memorydevices. See, for example, U.S. Pat. Nos. 5,541,871 (“NonvolatileFerroelectric Semiconductor Memory”) and 5,856,688(“Integrated CircuitMemory Devices Having Nonvolatile Single Transistor Unit CellsTherein”), which patents are also incorporated herein by reference forall purposes. It will be appreciated that in these devices, however, theremnant charge or polarization charge of the ferroelectric element isused to store information rather than electrons injected onto or removedfrom a floating gate by hot electron effects and/or tunneling. Instead,the charge differences are not differences in the number of electronstrapped on the gate but rather the polarization charge of the upperferroelectric capacitor.

It should also be mentioned that the prior art referenced in U.S. Pat.No. 5,541,871describes a basic structure consisting of a ferroelectriccapacitor in series with a gate capacitance, which are both planarstructures. As shown in FIG. 1(b), a memory cell 1′ includes a wordline10, a digitline 12, a transistor 14, and a ferroelectric capacitor 20,one plate of the ferroelectric capacitor forming the gate of thetransistor 14.

FIG. 1(c) illustrates a memory cell 1″, which includes the wordline 10,digitline 12, transistor 14, a high dielectric capacitor 30 and aferroelectric capacitor 32. It will be noted that the lower plate ofcapacitor 30 forms the control gate of the transistor 14.

The problem with this disclosed structure is that the ferroelectricelements have very high electric permittivities as, for instance, 80 and150 k. It will be appreciated that these permittivity values are 20 to40 times higher than that of silicon dioxide. It will also beappreciated that, if comparable thicknesses of materials as are used inconstructing the ferroelectric and conventional capacitors, only a smallfraction, e.g., 2% to 5%, of the voltage applied across the seriescapacitors will appear across the ferroelectric capacitor. Thus, if theferroelectric capacitor has a coercive voltage, Vc , i.e., the voltagerequired for programming, of 1 V or 3 V, then the total word linevoltage required for programming the memory cell will be on the order 20V to 150 V. It will be noted that these are far in excess of voltagesused on current CMOS-integrated circuits.

U.S. Pat. No. 5,856,688 seeks to solve this problem by using a “C”shaped floating gate and two control gates. One control gate is a plateof the ferroelectric capacitor and the other control gate is a plate ofanother capacitor fabricated using a high dielectric constant material.The two capacitors in series, one with a high dielectric constantferroelectric and the other with a high dielectric constant insulator,are used to program the ferroelectric capacitor at lower voltages. Sincethe capacitances are more or less comparable, the programming voltagewill divide more equally, resulting in a significant fraction across theferroelectric capacitor.

It should be mentioned that other repressed memory devices have beenproposed. For example, a repressed memory where the NVRAM function isprovided by a flash memory type structure for the gate of the transferdevice is described in the commonly assigned, copending applicationentitled “DRAM AND SRAM MEMORY CELLS WITH REPRESSED MEMORY” (Ser. No.(09/362,909, filed Jul. 29, 1999), which application is incorporatedherein by reference for all purposes. It will be appreciated that thesememories do not function like the shadow RAM disclosed in U.S. Pat.5,399,516 (“Method of Making a Shadow Ram Cell Having a Shallow TrenchEEPROM”), storing the same information on both memory planes.

In contrast, U.S. application Ser. No.09/385,380, describes a memorycell 1′″ having first and second operating modes. The memory cell 1′″includes a charge transfer transistor 14 having a gate adjacent to achannel region coupling source and drain regions, a digitline 12 coupledto one of the source and drain regions, a storage capacitor 16 coupledto the other of the source and drain regions, a ferroelectric capacitor32, and a wordline 10 coupled to the gate by the ferroelectric capacitor32. The polysilicon vertical interconnect connecting the ferroelectriccapacitor 32 with oxide layer covering the gate of the transistor 14forms an intrinsic capacitor 30. See FIG. 1(d). Data is written to andread out of the storage capacitor during the first operating mode, i.e.,a normal DRAM access speeds, and written to and read out of theferroelectric capacitor during the second mode of operation, i.e., atspeeds several times slower than normal DRAM access speeds.

It would be very desirable if a memory cell or device could be developedwith all of the positive features of DRAMS, i.e., cost, size, speed,availability, etc., which also is nonvolatile, i.e., maintains itsmemory state with power removed. It would be highly desirable to have amemory element and corresponding system that functions at speedscomparable to that of today's DRAMs. It would also be desirable if atleast one logic device could be implement using a modified form of thememory cell.

SUMMARY OF THE INVENTION

Based on the above and foregoing, it can be appreciated that therepresently exists a need in the pertinent art which mitigates theabove-described deficiencies.

In one aspect, the present invention provides a one transistor/onecapacitor (1T/1C) memory cell including a ferroelectric capacitoroperatively coupled to the gate electrode of a charge amplifier.Preferably, the ferroelectric capacitor has a small surface arearelative to the surface area of the gate electrode and, most preferably,the ferroelectric capacitor is an edge defined ferroelectric capacitor.In an exemplary embodiment, the charge amplifier is a transistor.

In another aspect, the present invention provides a memory cellincluding a charge amplifier having a gate adjacent to a channel regioncoupling source and drain regions, a digitline coupled to one of thesource and drain regions, a ground lead coupled to the other of thesource and drain regions, a ferroelectric capacitor coupled to the gate,and a wordline coupled to the ferroelectric capacitor. Advantageously,the charge amplifier can be a transistor. Preferably, the gate iscoupled to the ferroelectric capacitor by polysilicon, the junctionformed at the gate has an intrinsic capacitance, and the capacitance ofthe ferroelectric capacitor is based on the magnitude of the intrinsiccapacitance. Alternatively, the gate is coupled to the ferroelectriccapacitor by polysilicon, the junction formed at the gate has anintrinsic capacitance, and the physical size of the ferroelectriccapacitor is based on the magnitude of the intrinsic capacitance. Inthis case, the thickness of a ferroelectric material layer in theferroelectric capacitor can be based on the magnitude of the intrinsiccapacitance.

In yet another aspect, the present invention provides a onetransistor/one capacitor (1T/1C) memory cell array, wherein each of the1T/1C memory cells is a ferroelectric capacitor operatively coupled tothe gate electrode of a charge amplifier. Preferably, the chargeamplifier is a transistor and, most preferably, the charge amplifier isa CMOS transistor. In an exemplary embodiment, the memory cell array isN rows by M columns of memory cells, and wherein the each of the Mcolumns is defined by an associated digitline and an associated sourceline.

In still another aspect, the present invention provides a memory cellarray, including a plurality of memory cells organized as an array ofrows and columns, at least one of the memory cells being a non-volatilememory cell including a charge transistor having a gate opposing achannel region coupling source and drain regions, a digitline coupled tothe drain region, a source line coupled to the source region, aferroelectric capacitor which stores data coupled to the gate, awordline coupled to the ferroelectric capacitor, and a sense amplifiercoupled to the digitline of the at least one memory cell.

In another aspect, the present invention provides a processor basedsystem, including a processor, and a memory cell array coupled to theprocessor, the memory cell array including a plurality of memory cellsorganized as an array of rows and columns, at least one of the memorycells being a non-volatile memory cell including a charge amplifierincluding a gate opposing a channel region coupling source and drainregions, a digitline coupled to the drain region, a source line coupledto the source region, a ferroelectric capacitor coupled to the gate, awordline coupled to the ferroelectric capacitor, and a sense amplifiercoupled to the digitline of the at least one memory cell.

In a still further aspect, the present invention provides a memorymodule, including a substrate including a circuit board, a plurality ofmemory chips mounted on the die substrate, wherein one or more of thememory chips comprise a memory cell array fabricated on thesemiconductor chip communicating with a processor, the memory cell arrayincluding at least one non-volatile memory cell including aferroelectric capacitor operatively coupled to the gate of a chargeamplifier.

In still another aspect, the present invention provides a method forreading information from a one transistor/one capacitor (1T/1C) memorycell having a charge amplifier including a gate disposed adjacent to achannel region coupling source and drain regions, a digitline coupled todrain region, a source line coupled to the source region, aferroelectric capacitor coupled to the gate, and a wordline coupled tothe ferroelectric capacitor, the method including grounding the sourceline, asserting the wordline and digitline, amplifying the charge on theferroelectric capacitor, and determining the resultant charge on thedigitline.

In yet another aspect, the present invention provides a method forwriting information to a one transistor/one capacitor (1T/1C) memorycell having a charge amplifier including a gate disposed adjacent to achannel region coupling source and drain regions, a digitline coupled todrain region, a source line coupled to the source region, aferroelectric capacitor coupled to the gate, and a wordline coupled tothe ferroelectric capacitor, the method including asserting the sourceline, asserting the wordline to thereby apply a potential greater thanthe coercive voltage of the ferroelectric capacitor across theferroelectric capacitor and the charge amplifier.

In another aspect, the present invention provides a logic element,including N+1 source/drain regions, N channels, each channel couplingadjacent ones of the N+1 source/drain regions, N gates disposed adjacentto the N channels, N ferroelectric capacitors, each of the Nferroelectric capacitors coupled to a respective one of the N gates, Nwordlines, each of the N wordlines coupled to a respective one of the Nferroelectric capacitors, a digitline couple to an end one of the N+1source/drain regions, and a source line coupled to the other end one ofthe N+1 source/drain regions. Preferably, the logic element is operatedby assertion of all of the N wordlines. Advantageously, theferroelectric capacitors are edge defined ferroelectric capacitors.

BRIEF DESCRIPTION OF THE DRAWINGS

These and various other features and aspects of the present inventionwill be readily understood with reference to the following detaileddescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 (a) illustrates a first use of a ferroelectric capacitor in aconventional memory cell;

FIG. 1(b) illustrates a second use of a ferroelectric capacitor in aconventional memory cell;

FIG. 1 (c) illustrates a third use of a ferroelectric capacitor in aconventional memory cell;

FIG. 1(d) illustrates a fourth use of a ferroelectric capacitor in amemory cell;

FIG. 2(a) illustrates a NVRAM memory cell employing a ferroelectriccapacitor according to the present invention;

FIG. 2(b) illustrates a NVRAM memory cell array employing aferroelectric capacitor according to the present invention;

FIG. 3(a) illustrates selected portions of the components used in thememory cell depicted in FIGS. 2(a) and 2(b);

FIG. 3(b) illustrates the hysteresis characteristic of the ferroelectriccapacitor employed in the memory cell illustrated in FIGS. 2(a) and2(b);

FIG. 4 is a high-level block diagram of a memory array device which canbe fabricated using the memory cell depicted in FIG. 2(b);

FIG. 5 is a flow chart illustrating a method for accessing the memorycell depicted in FIG. 2(a);

FIGS. 6(a), 6(c) 6(e) illustrate the application of various voltages toselected portions of the circuitry illustrated in FIG. 2(a);

FIGS. 6(b), 6(d) 6(f) are hysteresis diagrams illustrating the effectson the ferroelectric capacitor of the voltages specified in FIGS. 6(a),6(c) 6(e), respectively;

FIG. 7 illustrates a NAND logic device which is formed using the basicNVRAM cell according to the present invention;

FIG. 8 is a flow chart illustrating the process flow for fabricating thememory cell illustrated in FIG. 2(a);

FIGS. 9(a) through 9(o) illustrate one of plan and section view of aworkpiece at various steps of the process flow illustrated in FIG. 8;

FIG. 10 is a plan view of a memory module having memory chipsconstructed according to the present invention; and

FIG. 11 is a high-level block diagram of a processor-based systememploying NVRAM memory chips constructed according to the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Illustrative embodiments and exemplary applications will now bedescribed with reference to the accompanying drawings which disclose theadvantageous teachings of the present invention.

While the present invention is described herein with reference toillustrative embodiments for particular applications, it should beunderstood that the invention is not limited thereto. Those havingordinary skill in the art and access to the teachings provided hereinwill recognize additional modifications, applications, and embodimentsand equivalent substitutions within the scope of the invention andadditional fields in which the present invention would be of significantutility.

FIG. 2(a) illustrates the basic transistor and memory cell 100electrical configuration according to the present invention, whichpreferably includes a transistor 114 connected between a source line 116and a digitline 112. In addition, a stacked capacitor gate structure isprovided, which includes a polysilicon gate capacitance 120 and a smallarea ferroelectric capacitor 118. More specifically, the memory cell 100according to the present invention includes a wordline 110, a digitline112, a transfer device, e.g., a transistor, 114, a source line 116 and aferroelectric capacitor 118. It will be appreciated that the transitionbetween the active region of the transfer device 114 and the polysiliconinterconnect 122 to the wordline 110 is an oxide layer 120 a, whichforms a gate capacitor 120. The basic memory cell 100 advantageously canbe employed in the memory cell array 142 illustrated in FIG. 2(b), whichis discussed in greater detail below.

A more detailed illustration of the transfer device 114, intrinsic gatecapacitor 120, polysilicon interconnect 122 and ferroelectric capacitor118 is provided in FIG. 3(a). It should be mentioned that theferroelectric capacitor 118 preferably includes Platinum (Pt) electrodes118 a, 118 c sandwiching a ferroelectric layer 118 b, which will bedescribed in greater detail below. The characteristics of theferroelectric layer 118 b and the gate oxide layer 120 a are listed inthe table below.

FIG. 3(b) illustrates a hysteresis loop characteristic of ferroelectricmaterial 118 b in comparison to the linear response of an oxide material120 a. In FIG. 3(b), V_(c) indicates coercive voltage, Q_(r) is remnantcharge, Q_(s) is saturation charge; the Y axis representscharge/centimeter squared in micro-coulombs. It will be appreciated thatas long as the applied voltage is less than V_(c), the charge willfollow the linear profiles indicated for layers 118 b and 120 a. OnceV_(c) has been exceeded, which corresponds to an applied voltage ofapproximately 1 V, the layer 118 b follows the hysteresis profile. Thus,by applying a relatively large voltage, e.g.,±5.0 V, the layer 118 bwill exhibit a remnant charge Q_(r), which advantageously can bepositive or negative. Since Q_(r) will effect the threshold voltageV_(th) of transistor 114, the polarity of Q_(r) can be determined byascertaining the effect on V_(th), as discussed in greater detail below.

TABLE I Gate Oxide Layer Ferroelectric Layer 118b Layer 120a Thickness800 Å 100 Å Relative Permittivity ε_(r) 80 4 Area 0.2 μm² 1.0 μm²Capacitance Per Unit Area 8.85 fF/μm² 3.54 fF/μm² Capacitance of Device1.77 fF 3.54 fF

It should also be mentioned that the ferroelectric characteristicsdepicted in FIG. 3(b) and Table I are that of a common ferroelectric,e.g., SrBiTaO, although other ferroelectric materials advantageously canbe used, as discussed in greater detail below.

It will be appreciated that since the effective dielectric constant ofthe ferroelectric material is so large, only a small area is requiredfor the ferroelectric capacitor 118. In contrast, the capacitor 120 hasthe normal gate capacitance of a minimum-sized transistor 114 in CMOStechnology. For purposes of illustration, the values presented in Table1 are characteristic of 1 micron CMOS technology employing 5 V powersupplies. It will be appreciated that these values advantageously can bescaled, as appropriate, to smaller CMOS technologies with criticaldimensions smaller than 1 micron. As mentioned above, the gatecapacitance, i.e., the intrinsic capacitance of capacitor 120, of atransistor 114 in this technology with a gate oxide thickness ofapproximately 100 Å is about 3.3 fF.

As mentioned above, the charge storage element of a ferroelectric memorycell consists of a ferroelectric film sandwiched between two electrodes.Lead zirconate titanates, PbZr_(x)Ti_(1-x)O₃ (PZT) with x=0.4-0.53 aremost studied materials for the ferroelectric film. It will beappreciated that this is because PZT films with thickness from 500 to4000 Å can fill the ferroelectric material requirements to a substantialdegree. Furthermore, it has been shown that PZT film processing can bedone in combination with standard integrated circuit processing, asdiscussed in the article by R. Cuppens, et al., entitled “Ferroelectricsfor Non-volatile Memories” (Microelectronic Engineering, 19 (1992), pp.245-252, 1992). Other thin-film materials potentially usable fornonvolatile memory devices include BaMgF₄ and Bi₄Ti₃O₁₂ for applicationwith the ferroelectric material gate insulator in a field effecttransistor (FET). Moreover, BaTiO₃, SrTiO₃ and (Sr,Ba)TiO₃advantageously can be employed for application as dielectrics in DRAMs.

Another important class of ferroelectric materials is the bismuth(Bi)-layer oxides. Bi-layer ferroelectric oxides have large polarizationalong the a or b axis, but no or little polarization along the c axis.Bi₄Ti₃O₁₂ is a typical bi-layer ferroelectric material. However, theobtained remnant polarization is very small, i.e., less than 10 μC/cm²and fatigue endurance is less than optimal. Recently, other types ofbi-layer oxides, such as SrBi₂Ta₂O₉ or SrBi₂Nb₂O₉hve demonstratedacceptable endurance. Amanuma, et al., recently reported a simplesolution deposition process of SrBi₂Ta₂O₉ (SBT) thin films in thearticle entitled “Preparation and Ferroelectric Properties of SrBi₂Ta₂O₉Thin Films” (Appl. Phys. Lett., 66 (2), pp. 221-223, 1995).

Referring back to FIG. 3(a), the ferroelectric capacitor 118 isillustrated as a capacitor on top of the gate of the transistor 114,which is connected to the gate of transistor 114 by polysiliconinterconnect 122, which is, in an exemplary case, approximately 2000 Åthick. Preferably, the ferroelectric capacitor 118 is fabricated bydepositing a ferroelectric material between two Pt plates or electrodes,one of the electrodes, e.g., electrode 118 a, being a vertical Ptwordline. The ferroelectric capacitor 118 advantageously has aneffective plate area of only about one-fifth that of the gate oxidecapacitor 120. Moreover, the ferroelectric dielectric 118 b willtypically be thicker, approximately 800 Å, than the gate oxide 120 a,approximately 100 Å. It will be appreciated that by properly sizing theferroelectric capacitor 118 and the intrinsic gate capacitor 120, thegate oxide capacitance and the ferroelectric capacitances can be madecomparable. Thus, when the coercive or programming voltage V_(c) of theferroelectric capacitor 118 is on the order of 1 V, then the memory cell100 can be programmed with a voltage as low as ±5 V. It will beappreciated that both of these values are consistent with and, in fact,less than used in 1 micron flash memory CMOS technology.

Thus, one preferred embodiment of the present invention is a onetransistor/one capacitor (1T/1C) memory cell including a ferroelectriccapacitor operatively coupled to the gate electrode of a chargeamplifier. Preferably, the ferroelectric capacitor has a small surfacearea relative to the surface area of the gate electrode and, mostpreferably, the ferroelectric capacitor is an edge defined ferroelectriccapacitor, i.e., a capacitor formed by running the ferroelectric filmover a step in the workpiece and then anisotropically etching the filmin the vertical direction. In an exemplary embodiment, the chargeamplifier is a transistor.

An exemplary embodiment according to the present invention provides amemory cell including a charge amplifier having a gate adjacent to achannel region coupling source and drain regions, a digitline coupled toone of the source and drain regions, a ground lead coupled to the otherof the source and drain regions, a ferroelectric capacitor coupled tothe gate, and a wordline coupled to the ferroelectric capacitor.Advantageously, the charge amplifier can be a transistor. Preferably,the gate is coupled to the ferroelectric capacitor by polysilicon, thejunction formed at the gate has an intrinsic capacitance, and thecapacitance of the ferroelectric capacitor is based on the magnitude ofthe intrinsic capacitance. Alternatively, the gate is coupled to theferroelectric capacitor by polysilicon, the junction formed at the gatehas an intrinsic capacitance, and the physical size of the ferroelectriccapacitor is based on the magnitude of the intrinsic capacitance. Inthis case, the thickness of a ferroelectric material layer in theferroelectric capacitor can be based on the magnitude of the intrinsiccapacitance. In an exemplary case, the ferroelectric capacitor is adielectric layer of lead zirconate titanate (PZT). Most preferably, thePZT forming the ferroelectric capacitor is of the formPbZr_(x)Ti_(1-x)O₃ with x ranging between 0.4 and 0.53

Referring now to FIG. 2(b), the memory array 142 advantageously can beformed from the NVRAM memory cell illustrated in FIG. 2(a). Preferably,the memory cell array 142 includes a plurality of NVRAM memory cells,e.g., cells 100 a, 100 b, 100 c, connected to one another by a commonword line W1. Each of the NVRAM memory cells, e.g., NVRAM memory cell100 a, advantageously can be addressed by a corresponding digit line,e.g., digit line D1, which preferably addresses other VRAM memory cells,e.g., cell 100 d, and which can be recharged for read out via a pulluptransistor, e.g., transistor T1. It will be appreciated that transistorT1 is switched for readout in the normal manner. In addition, the sourceterminals for a column of memory cells 100 are connected to a ground viaa switch S1. It will be appreciated that all of the switchesadvantageously can be closed during a read operation of the memory array142 but can be selectively operated during a write operation, i.e., inorder to write data to a selected one of the memory cells in the memoryarray 142, the corresponding source line is asserted.

Thus, an exemplary one transistor/one capacitor (1T/1C) memory cellarray is provided by the present invention. In the exemplary case underdiscussion, each of the 1T/1C memory cells is a ferroelectric capacitoroperatively coupled to the gate electrode of a charge amplifier.Preferably, the charge amplifier is a transistor and, most preferably,the charge amplifier is a CMOS transistor. In an exemplary embodiment,the memory cell array is N rows by M columns of memory cells, andwherein the each of the M columns is defined by an associated digitlineand an associated source line.

Referring to FIG. 4, an exemplary DRAM circuit 140 is illustrated. TheDRAM 140 contains a memory cell array 142, row and column decoders 144,148 and a sense amplifier circuit 146. The memory cell array 142consists of a plurality of memory cells 100 (constructed as illustratedin FIG. 2(a)) whose word lines 110 and digitlines 112 are commonlyarranged into rows and columns, respectively. The digitlines 112 of thememory array 142 are connected to the sense amplifier circuit 146, whileits word lines 110 are connected to the row decoder 144. The sourcelines for all memory cells 100 is grounded, preferably by source line116. Address and control signals are input into the DRAM 140 andconnected to the column decoder 148, sense amplifier circuit 146 and rowdecoder 144 and are used to gain read and write access, among otherthings, to the memory array 142.

The column decoder 148 is connected to the sense amplifier circuit 146via control and column select signals. The sense amplifier circuit 146receives input data destined for the memory array 142 and outputs dataread from the memory array 142 over input/output (I/O) data lines. Datais read from the cells of the memory array 142 by activating a word line(via the row decoder 144), which couples all of the memory cells 100corresponding to that word line 110 to respective digitlines 112, whichdefine the columns of the array. One or more of the digitlines 112 arealso activated. When a particular wordline-digitline pair is activated,the sense amplifier circuit 146 connected to a digitline column detectsand amplifies the data bit impressed on the capacitor 118 of the memorycell 100 to its respective digit line 112 by measuring the potentialdifference between the activated digitline and a reference line whichmay be an inactive bit line. The operation of DRAM sense amplifiers isdescribed, for example, in U.S. Pat. Nos. 5,627,785, 5,280,205, and5,042,011, all of which are assigned to Micron Technology Inc., and allof which are incorporated herein by reference for all purposes.

Thus, a memory cell array according to the present invention includes aplurality of memory cells organized as an array of rows and columns,where at least one of the memory is a non-volatile memory cell having acharge transistor having a gate opposing a channel region couplingsource and drain regions, a digitline coupled to the drain region, asource line coupled to the source region, a ferroelectric capacitorwhich stores data coupled to the gate, a wordline coupled to theferroelectric capacitor, and a sense amplifier coupled to the digitlineof the at least one memory cell. Preferably, the ferroelectric capacitorhas a surface area which is small relative to the surface area of thegate. Most preferably, the ferroelectric capacitor is an edge definedferroelectric capacitor. In an exemplary case, the data is written intothe ferroelectric capacitor when the wordline and source line areasserted and the data is read from the non-volatile memory cell when thewordline, the digitline and the source line are asserted. In anexemplary case, an asserted source line is a grounded source line.Preferably, the charge amplifier amplifies the charge stored in theferroelectric capacitor by at least one order of magnitude. In anyevent, the charge amplifier amplifies the charge stored in theferroelectric capacitor by a predetermined gain factor. The chargeamplifier advantageously can be a transistor.

The operation of the memory cell 100 according to the present inventionwill now be described while referring to FIGS. 2(b), 5, and 6(a)-6(f).

Referring now to FIG. 5, after the system in which the memory device 142is located is initialized, a check is first performed to determinewhether the memory cells 100 are being accessed for a read operationduring step 502. If the answer is affirmative, all of the source linesare coupled to ground potential during step 504 by operation of switchesS1, S2, etc., and then a read operation is performed in the normalmanner for a DRAM, i.e., the wordline and digitlines for a particularmemory cell are asserted, during step 506, which read operation is wellknown to one of ordinary skill in the art and will not be describedfurther in the interest of brevity. However, the principal which permitsthe memory cell 100 to be read out normally will be discussed below.Irrespective of whether step 506 or step 510 (discussed below) isperformed, step 502 is then repeated. It will be appreciated that aslong as the voltage applied to the wordline 110 remains in the normaloperating range of the transistor 114, e.g., 3 V, the coercive voltageof the ferroelectric capacitor 118 is not exceeded and the state of theferroelectric capacitor is unchanged. See FIGS. 6(a) and 6(b).

When the answer at step 502 is negative, the source line for all of thememory cells are deasserted, i.e., the switches S1, S2, etc., are openedduring step 508. Then, a voltage in excess of the coercive voltage Vcfor the ferroelectric capacitor 118 is applied to the wordline 110 ofmemory cell 100 while the source 116 for the selected cell(s) is(are)grounded and all other source lines 112 are open circuited. A voltage inexcess of the coercive voltage Vc for the ferroelectric capacitor 118 isthus applied by assertion of the wordline 110 and source line 116 forthe selected memory cell. It will be appreciated that the value storedin the ferroelectric capacitor 118 is determined by the polarity of thevoltage applied. For example, as illustrated in FIGS. 6(c) and 6(d),when a +5 V potential is applied to wordline 110, a value correspondingto one digital level, e.g., “one,” is stored in the ferroelectriccapacitor 118. In contrast, application of a −5 V potential to thewordline results in the opposite digital level i.e., “zero,” beingstored in the ferroelectric capacitor 118, as illustrated in FIGS. 6(e)and 6(f). It will also be appreciated that the correspondence betweenthe stored charge polarity and the digital value is arbitrary; apositive potential advantageously can be used to write a digital “zero”into ferroelectric capacitor 118. It should be mentioned that the timeneeded to write to the memory cell 100 in memory array 142 issubstantially to the read time for the memory cell.

Thus, the read operation is achieved by driving the word line to somevoltage less than the coercive or programming voltage, and reading theconductivity of the transistor. The capacitance of the wordline 110 ofeach memory cell 100 advantageously be comparable to that in DRAMs sincethe gate capacitances are in series and, in the exemplary case underdiscussion, about 1 fF. It should be mentioned at this point that unlikethe transistor in a conventional DRAM, the transistor 114 is not apassive transfer gate, but rather provides gain and chargemultiplication. If the charge differences on the ferroelectric capacitor118 are 10 μC/cm², and the area is 2×10⁻⁹ cm², then the chargedifference in the memory cell 100 itself is 2 fC. However, it will beappreciated that this charge is multiplied during the read operation bythe transistor 114. Thus, if the difference in charge states of theferroelectric capacitor 118 results in a drain current difference of 100uA in the transistor 114 during a read cycle of 1 nanosecond (ns), thenthe differences in charge on the data or bit line 112 during readoperation is approximately 100 fC. It will be appreciated that thisvalue is comparable to that obtained using current DRAMs equipped with30 ferroelectric capacitor storage capacitors and 3 V potentialdifferences.

Thus, one exemplary embodiment of the present invention is a method forreading information from a one transistor/one capacitor (1T/1C) memorycell having a charge amplifier including a gate disposed adjacent to achannel region coupling source and drain regions, a digitline coupled todrain region, a source line coupled to the source region, aferroelectric capacitor coupled to the gate, and a wordline coupled tothe ferroelectric capacitor, the method including grounding the sourceline, asserting the wordline and digitline, amplifying the charge on theferroelectric capacitor, and determining the resultant charge on thedigitline. Preferably, a voltage less than the coercive voltage of theferroelectric capacitor is asserted on the wordline while apredetermined voltage, e.g., V_(DD), is asserted on the digitline.

A complementary embodiment of the present invention is a method forwriting information to a one transistor/one capacitor (1T/1C) memorycell having a charge amplifier including a gate disposed adjacent to achannel region coupling source and drain regions, a digitline coupled todrain region, a source line coupled to the source region, aferroelectric capacitor coupled to the gate, and a wordline coupled tothe ferroelectric capacitor, the method including asserting the sourceline, and asserting the wordline to thereby apply a potential greaterthan the coercive voltage of the ferroelectric capacitor across theferroelectric capacitor and the charge amplifier.

It will be appreciated that several ferroelectric capacitor/transistorpairs advantageously can be fabricated into a NAND gate 175, asillustrated in FIG. 7. In the NAND gate 175, a plurality offerroelectric capacitor FCA, FCB, FCC, and FCD are coupled to the gatesof respective transistors TA, TB, TC, and TD. From FIG. 7, it will benoted that the output of NAND gate 175 can be sensed on digitline 179when all of the gates are asserted. In an exemplary case, all of thegates of transistor TA-TD are asserted when the wordlines 177, e.g.,wordlines W1, W2, W3, and W4, are all asserted. The source of transistorTA advantageously can be coupled to ground.

Stated another way, a logic device according to the present inventionincludes N+1 source/drain regions, N channels, each channel couplingadjacent ones of the N+1 source/drain regions, N gates disposed adjacentto the N channels, N ferroelectric capacitors, each of the Nferroelectric capacitors coupled to a respective one of the N gates, Nwordlines, each of the N wordlines coupled to a respective one of the Nferroelectric capacitors, a digitline couple to an end one of the N+1source/drain regions, and a source line coupled to the other end one ofthe N+1 source/drain regions. Preferably, the logic element is operatedby assertion of all of the N wordlines. Advantageously, theferroelectric capacitors are edge defined ferroelectric capacitors.

As previously mentioned, the ferroelectric capacitor 118 according tothe present invention advantageously can be an edge-definedferroelectric capacitor. Fabrication of the ferroelectric capacitor willbe discussed with respect to FIG. 8. However, before describing anexemplary process for the manufacture of memory cell 100, a brief reviewof the currently available technology, from which preferred methodologyfor the fabrication of one type of edge-defined capacitors, will bepresented. It will be appreciated that the method discussed immediatelybelow advantageously may be applied to other types of edge-definedcapacitors.

As discussed above, the charge storage element 118 of a ferroelectricmemory cell 100 consists of a ferroelectric film 118 b sandwichedbetween two electrodes 118 a, 118 c. Lead zirconate titanates,PbZr_(x)Ti_(1-x)O₃ (PZT) with x=0.4-0.53 are most studied materials formemory applications, since PZT films with thickness from 500 to 4000 Åcan fill the ferroelectric requirements to a substantial degree. Otherthin-film materials which advantageously can be employed in nonvolatilememory devices include BaMgF₄ and Bi₄Ti₃O₁₂ for application with theferroelectric material gate insulator in FET. BaTiO₃, SrTiO₃ and(Sr,Ba)TiO₃ have demonstrated usefulness in application as dielectricsin DRAMs.

It will be appreciated that the use of sputtering for the deposition ofPZT, Bi₄Ti₃O₁₂ and oxides was developed in the 1970s. RF diode,magnetron and ion-beam sputtering techniques have all been used withmetallic and oxide targets. However, it is difficult to prepare large,dense ceramic targets, which are necessary to obtain uniform layers onlarge substrates. Therefore, reactive sputtering using metallic targetsis more commonly used. Because of the volatility of Pb and PbO, thecontrol of stoichiometry is a major problem, which problem can beminimized by the use of multi-target or multi-target ion beamsputtering. This technique is suitable for edge-defined capacitors.

Alternative techniques for the deposition of PZT films include MetalOrganic Deposition (MOD) and a sol-gel process. With these processes,the ferroelectric film is formed by the thermal decomposition of asolution of organo metallic compounds which can be spun onto thesubstrate. The subsequent drying, firing and annealing processes of thefilm strongly influence the morphology and ferroelectric properties ofthe PZT. It should be mentioned that thicker films can be obtained byrepeating the spinning, drying and firing sequence. The main advantageof these processes is the ease by which complex oxide films can beprepared. These techniques are applicable to edge-defined capacitors.

Yet another technique which is useful in the fabrication offerroelectric capacitors is Organo Metallic Chemical Vapor Deposition(OMCVD), which offers advantages such as good step coverage, highdeposition rate, and low-temperature deposition, and is particularlysuitable to a type of edge-defined capacitors which might haveferroelectric material on a sidewall. Additionally, an ozone jetreactive evaporation technique has been developed to deposit thin leadzirconate titanate films. It will be appreciated that because lead has alow affinity with oxygen and high volatility, lead may re-evaporate fromthe film and/or diffuse into the electrode and leave lead vacancies inPZT films. In a sol-gel or sputtering process, excess lead is oftenadded to compensate for this lead loss. However, problems resulting fromlead diffusion into surrounding electrode material was not elevated bythis practice, i.e., the use of excess lead during sputtering. For achemical vapor deposition (CVD) process, since the wafer is being heatedduring film deposition, unreacted lead may easily diffuse into theelectrode material. To mitigate the problems associated with metalliclead or less oxidized lead in the film, it was common to employhigh-concentration ozone to oxidize lead vapor at low temperature, andobtain a fully oxidized amorphous films by the co-evaporation method.Rapid thermal annealing (RTA), 650° C. for 120 seconds in oxygenambient, is then used to crystallize the amorphous film into perovskitestructure without lead re-evaporation or lead diffusion. It will beappreciated that this technique is particularly well suited to thefabrication of edge-defined capacitors. Other methods for thepreparation of ferroelectric thin films include molecular beam epitaxy(MBE), although application of this fabrication method makes itdifficult to comply with competing requirements of IC productionprocesses such as large wafers, high throughput, etc.

It will also be appreciated that an important parameter, one which willinfluence the properties of the ferroelectric capacitors, are theelectrodes. Because of the chemical reactivity of PZT and relatedmaterials and relatively high processing temperatures (>600° C.), a veryinert bottom electrode is required. In general, Pt-based electrodes areused which are deposited onto silicon oxide or nitride by sputteringusing an adhesive layer such as TiN, Ti, or the two in combination.Although relatively inert, the Pt bottom electrode does affect themorphology and the ferroelectric properties of the PZT films and relatedmaterials.

It has been reported in the literature that better hysteresis propertiesof PZT films (by sol-gel process) are achievable when the PZT isdeposited onto a multilayer stack of Pt/RuO₂PZT/RuO₂/Pt. It isspeculated that the microstructure, in particular the grain size of PZT,of the PZT films were influenced by RuO₂. Beneficially, films withsmaller grain sizes had larger coercive fields. In addition, the effectof microstructure on the electrical characteristics of sol-gel derivedPZT thin films deposited on a Pt electrode have been demonstrated usingdifferent solutions, i.e., films with different degree of preferredorientation of the perovskite crystal as well as different grain sizewere obtained. It is believed that while smaller grains are generallydesired to obtain good device to device uniformity, the electricalproperties of these smaller grains require further evaluation beforethey can be deemed suitable for either NVRAM MEMORY CELL, in particular,or DRAM applications, in general.

As previously mentioned, another class of ferroelectric materials is thebismuth (Bi)-layer oxides. Bi-layer ferroelectric oxides have largepolarization along the a or b axis, but no or little polarization alongthe c axis. Bi₄Ti₃O₁₂ is a typical bi-layer ferroelectric, and thesynthesis of this material has been reported. However, the obtainedremnant polarization is very small, less than 10 μC/cm² and fatigueendurance is poor. Recently, other types of bi-layer oxides, such asSrBi₂Ta₂O₉ or SrBi₂Nb₂O₉ were found to have good endurance.

Referring now to FIG. 8, a process flow for integration of ferroelectriccapacitors into the memory devices 140 will now be described. It shouldbe mentioned that the process flow is geared to produce a memory cellpair; the process advantageously can be employed in fabricating thememory array 142 or the NAND gate 175 by proper selection of variousprocess masks. It should also be mentioned at this point that suchintegration should not degrade the ferroelectric properties of the film.One example of process integration with a stacked capacitor structurewas shown by Onish, et al., in the article entitled “A Half-MicronFerroelectric Memory Cell Technology with Stacked Capacitor Structure,”(1994 IEDM Digest, pp. 843-846, 1994). However, an alternative exemplaryprocess flow is described below which advantageously can be employed infabricating the ferroelectric capacitors within spacer-defined wordlines518. It should also be mentioned that the process flow described belowadvantageously can be employed in fabricating memory cell pairs sharinga common digitline.

The process flow starts with a workpiece 500, e.g., a wafer fragment,following well formation and growth of a thin (e.g.,˜10 nm) pad ofthermal oxide 502 followed by deposition of a thick pad of nitride 504(˜0.2 μm) for formation of STI (shallow trench isolation) during step600. During step 602, resist is applied and masked, isolation trenchesare etched and filled with oxide 506 and the structure is subjected tochemical mechanical processing (CMP), as in other, conventional processflows. This leaves the structure as shown in FIGS. 9(a) and 9(b).

During step 604, the pad nitride 504 and oxide 502 is removed to exposebare silicon in the active areas, preferably recessed relative to theSTI surface. Next, during step 606, gate oxide 508 is grown, prior todepositing polysilicon gate material 510 and subsequent CMP finishing toleave structure as shown in FIGS. 9(c) and 9(d).

During step 608, a resist 512 is applied, the gate pattern is exposed,and the wafer is etched to produce the intermediate product depicted inFIGS. 9(e) and 9(f).

During step 610, the resist 512 is removed and the source/drain pockets514 are ion implanted and annealed. During optional step 612, the wafercan be finished to restore surface planarity by chemical vapordeposition (CVD) of intrinsic polysilicon 516 followed by another roundof CMP. During step 614, the ferroelectric capacitor 118 is formed bydepositing a Pt layer 118 a, a ferroelectric material layer 118 b, and afinal Pt cap layer 118 c on the surface of the intrinsic polysilicon 516and gate material 510. It will be appreciated that any of the depositionprocesses discussed in detail above advantageously can be employed indepositing the ferroelectric material layer. Moreover, the ferroelectriccapacitor material 118 b advantageously can be chosen from thenon-limiting list of materials presented above. During step 616,intrinsic polysilicon 516′ is deposited to a thickness equal to thedesired height of the final spacer defined word lines (e.g., 0.2 μm).Then a resist 512′ is applied and masked to define word line edgepattern illustrated in FIGS. 9(g) and 9(h) during step 618.

During step 620, the intrinsic polysilicon mandril material isdirectionally etched, preferably stopping on underlying Pt cap layer 118c and then the resist 512′ is removed. During step 622, a suitable wordline conductor 518 (e.g., doped polysilicon, refractory metal orsilicide) is deposited by CVD and then directionally etched to leaveconductor 518 as a spacer on the vertical edges of the mandril, i.e., toform edge-defined ferroelectric capacitors as shown in FIGS. 9(i) and9(j).

During step 624, a suitable selective etchant is employed to removeintrinsic polysilicon 516 mandril material. In step 626, the exposedPt-ferroelectric material-Pt sandwich 118 a, 118 b, 118 c is etchedaway. Moreover, during step 628, the workpiece 500 is selectively etchedto remove any remaining intrinsic polysilicon 516 over the source/drainpockets 514, leaving the structure shown in FIGS. 9(k) and 9(l).

Finally, during step 630, a thick oxide interlayer dielectric isdeposited, planarized to form contact holes and wiling levels as inconventional processing. It will be appreciated that when the wordlines110 are formed, these wordlines will be considerably wider than theunderlying ferroelectric capacitor 118, as illustrated in FIG. 9(m). Itwill be appreciated that FIG. 9(n), which is a schematic diagram of thememory cells illustrated in FIG. 9(m) is included to orient the reader.

It should also be mentioned that the process discussed aboveadvantageously could be employed in fabricating other structures. Forexample, the memory array 142 advantageously could be fabricated as anumber of subarrays, each having an associated block select switch,e.g., BS1, BS2, etc., serially coupling the local wordlines LW1, LW2,etc., to a global wordline GWL, as illustrated in FIG. 9(o).

FIG. 10 is plan view of a memory module 600 having memory chips 60-68including semiconductor memory devices constructed in accordance withthe present invention. That is, chips 60-68 have a NVRAM cell such asdescribed in connection with FIG. 2. Memory module 600 is a SIMM (singlein line memory module) having nine memory chips (IC's) 60-68 aligned onone side of a printed circuit board substrate. The number of such memorychips in the SIMM typically will vary between 3 to 9. The circuit board601 has an edge connector 602 along one longitudinal edge to permit itto plug into a memory socket on a computer motherboard of conventionaldesign (not shown). A wiring pattern (not shown), which can be aconventionally known design for this purpose, is formed on the board 601and connects the terminals or leads shown comprising the edge connector602 to the memory chips 60-68. Small ceramic decoupling capacitors 69are also mounted on substrate 601 to suppress transient voltage spikes.Other than the memory device structures formed in accordance with theinventive method and used in memory chips 60-68, the general layout ofthe SIMM 600 can be a conventional construction.

Thus, another exemplary embodiment of the present invention is a memorymodule, including a substrate in, for example, a circuit board, aplurality of memory chips mounted on the die substrate, wherein one ormore of the memory chips comprise a memory cell array fabricated on asemiconductor chip for communicating with a processor, the memory cellarray including at least one non-volatile memory cell including aferroelectric capacitor operatively coupled to the gate of a chargeamplifier. Preferably, the gate is coupled to the ferroelectriccapacitor by polysilicon, the junction formed at the gate has anintrinsic capacitance, and the capacitance of the ferroelectriccapacitor is based on the magnitude of the intrinsic capacitance.Alternatively, the gate is coupled to the ferroelectric capacitor bypolysilicon, the junction formed at the gate has an intrinsiccapacitance, and the physical size of the ferroelectric capacitor isbased on the magnitude of the intrinsic capacitance. Preferably, theferroelectric capacitor includes a dielectric layer of lead zirconatetitanate (PZT), which advantageously can be of the formPbZr_(x)Ti_(1-x)O₃ with x ranging between 0.4 and 0.53. In an exemplarycase, the non-volatile memory cell includes the charge amplifier havinga gate disposed adjacent to a channel region coupling source and drainregions, a digitline coupled to drain region, a source line coupled tothe source region, the ferroelectric capacitor coupled to the gate, anda wordline coupled to the ferroelectric capacitor.

FIG. 11 is a block diagram of a processor-based system 400 utilizing amemory 412 constructed in accordance with the present invention. Thatis, the memory 412 utilizes the memory cells 100 illustrated in FIG.2(a), which advantageously can be provided in the form of the memorydevice 140. The processor-based system 400 may be a computer system, aprocess control system or any other system employing a processor andassociated memory. The system 400 includes a central processing unit(CPU) 402, e.g., a microprocessor, that communicates with the RAM 412and an I/O device 408 over a bus 420. It must be noted that the bus 420may be a series of buses and bridges commonly used in a processor-basedsystem, but for convenience purposes only, the bus 420 has beenillustrated as a single bus. A second I/O device 410 is illustrated, butis not necessary to practice the invention. The processor-based system400 also includes an additional memory 414, which could be either aread-only memory (ROM) or another of the memory devices 140 according tothe present invention, since, as discussed above, the memory cells arenon-volatile devices. The processor based system may include peripheraldevices such as a floppy disk drive 404, a compact disk (CD) ROM drive406, a display (not shown), a key board (not shown), and a mouse (notshown), that communicate with the CPU 402 over the bus 420 as is wellknown in the art.

It should be noted that since the memories 412 and 414 advantageouslycan be the memory device 140 according to the present invention, thenumber of discrete memory devices needed for the processor based system400 can be reduced. Stated another way, since the memory array 142according to the present invention is populated by non-volatile memorycells 100, a predetermined portion of the memory device 142advantageously can be employed as the ROM in the processor based system400.

Thus, another preferred embodiment of the present invention includes aprocessor based system, including a processor, and a memory cell arraycoupled to the processor, the memory cell array including a plurality ofmemory cells organized as an array of rows and columns, at least one ofthe memory cells being a non-volatile memory cell including a chargeamplifier including a gate opposing a channel region coupling source anddrain regions, a digitline coupled to the drain region, a source linecoupled to the source region, a ferroelectric capacitor coupled to thegate, a wordline coupled to the ferroelectric capacitor, and a senseamplifier coupled to the digitline of the at least one memory cell.Preferably, data is written into the ferroelectric capacitor when thewordline and the source line are both asserted, while data is read outof the memory cell when the wordline, the digitline and the source lineare asserted, under the control of the processor. Advantageously, theferroelectric capacitor is an edge defined ferroelectric capacitor.Preferably, the ferroelectric capacitor is a dielectric layer of leadzirconate titanate (PZT) and, most preferably, the PZT forming theferroelectric capacitor is of the form PbZr_(x)Ti_(1-x)O₃ with x rangingbetween 0.4 and 0.53.

It should again be mentioned that all of the patents, patentapplications, and articles cited to or discussed above are incorporatedherein by reference for all purposes.

Although presently preferred embodiments of the present invention havebeen described and illustrated, it should be clearly understood thatmany variations and/or modifications can be made without departing fromspirit and scope of the invention. Accordingly, the invention is notlimited by the foregoing description but is only limited by the scope ofthe attached claims.

What is claimed is:
 1. A one transistor/one capacitor (1T/1C) memorycell comprising an edge defined ferroelectric capacitor operativelycoupled to the gate electrode of a charge amplifier transistor by apolysilicon interconnect, wherein the edge defined ferroelectriccapacitor is in a stacked alignment with an active gate oxide channelregion of the transistor.
 2. The memory cell as recited in claim 1,wherein the ferroelectric capacitor has a surface area which is apredetermined percentage of the surface area of the gate electrode. 3.The memory cell as recited in claim 1, wherein the ferroelectriccapacitor comprises an edge defined ferroelectric capacitor.
 4. Thememory cell as recited in claim 1, wherein the charge amplifiertransistor comprises a CMOS transistor.
 5. A memory cell comprising: acharge amplifier comprising a gate adjacent to a channel region couplingsource and drain regions; a digitline coupled to one of the source anddrain regions; source line coupled to the other of the source and drainregions; an edge defined ferroelectric capacitor coupled to the gate bya polysilicon interconnect; and a wordline coupled to the edge definedferroelectric capacitor, wherein the edge defined ferroelectriccapacitor is in a stacked alignment with an active oxide channel regionof the charge amplifier.
 6. The memory cell as recited in claim 5,wherein the charge amplifier comprises a transistor.
 7. The memory cellas recited in claim 5, wherein the charge amplifier comprises a CMOStransistor.
 8. The memory cell as recited in claim 5, wherein: thejunction formed at the gate has an intrinsic capacitance; and thecapacitance of the ferroelectric capacitor is based on the magnitude ofthe intrinsic capacitance.
 9. The memory cell as recited in claim 5,wherein: the junction formed at the gate has an intrinsic capacitance;and the physical size of the ferroelectric capacitor is based on themagnitude of the intrinsic capacitance.
 10. The memory cell as recitedin claim 9, wherein the thickness of a ferroelectric material layer inthe ferroelectric capacitor is based on the magnitude of the intrinsiccapacitance.
 11. A memory cell comprising: a charge amplifier comprisinga gate opposing a channel region coupling source and drain regions; adigitline coupled to the drain region; a source line coupled to thesource region; an edge defined ferroelectric capacitor coupled to thegate by a polysilicon interconnect, the edge defined ferroelectriccapacitor being configured to store data; and a wordline coupled to thegate by the edge defined ferroelectric capacitor, wherein the edgedefined ferroelectric capacitor is in a stacked alignment with an activegate oxide channel region of the charge amplifier.
 12. The memory cellas recited in claim 11, wherein the charge amplifier is a CMOStransistor.
 13. The memory cell as recited in claim 11, wherein theferroelectric capacitor has a surface area which is a predeterminedpercentage of surface area of the gate of the charge amplifier.
 14. Thememory cell as recited in claim 11, wherein: the junction formed at thegate has an intrinsic capacitance; and the capacitance of theferroelectric capacitor is based on the magnitude of the intrinsiccapacitance.
 15. The memory cell as recited in claim 11, wherein: thejunction formed at the gate has an intrinsic capacitance; and thephysical size of the ferroelectric capacitor is based on the magnitudeof the intrinsic capacitance.
 16. The memory cell as recited in claim11, wherein the ferroelectric capacitor is an edge defined ferroelectriccapacitor.
 17. The memory cell as recited in claim 16, wherein the edgedefined ferroelectric capacitor comprises a dielectric layer of leadzirconate titanate (PZT).
 18. The memory cell as recited in claim 11,wherein the ferroelectric capacitor comprises a dielectric layer of leadzirconate titanate (PZT).
 19. The memory cell as recited in claim 18,wherein the PZT comprising the ferroelectric capacitor is of the formPbZr_(x)Ti_(1-x)O₃ with x ranging between 0.4 and 0.53.
 20. A onetransistor/one capacitor (1T/1C) memory cell array, wherein each of the1T/1C memory cells comprises an edge defined ferroelectric capacitoroperatively coupled to the gate electrode of a charge amplifiertransistor by a polysilicon interconnect, wherein the edge definedferroelectric capacitor is in a stacked alignment with an active gateoxide channel region of the transistor.
 21. The memory cell array asrecited in claim 20, wherein the charge amplifier transistor comprises aCMOS transistor.
 22. The memory cell array as recited in claim 20,wherein the memory cell array comprises N rows by M columns of memorycells, and wherein the each of the M columns is defined by an associateddigitline and an associated source line.
 23. The memory cell array asrecited in claim 20, wherein the surface area of the ferroelectriccapacitor is a predetermined percentage of the surface area of the gateof the charge amplifier.
 24. The memory cell array as recited in claim23, wherein the ferroelectric capacitor is an edge defined ferroelectriccapacitor.
 25. The memory cell array as recited in claim 24, wherein theedge defined ferroelectric capacitor comprises a dielectric layer oflead zirconate titanate.
 26. A memory cell array, comprising: aplurality of memory cells organized as an array of rows and columns, atleast one of the memory cells being a nonvolatile memory cellcomprising: a charge transistor comprising a gate opposing a channelregion coupling source and drain regions; a digitline coupled to thedrain region; a source line coupled to the source region, an edgedefined ferroelectric capacitor coupled to the gate by a polysiliconinterconnect; a wordline coupled to the edge defined ferroelectriccapacitor; and a sense amplifier coupled to the digitline of the atleast one memory cell, wherein the edge defined ferroelectric capacitoris in a stacked alignment with an active gate oxide channel region ofthe transistor.
 27. The memory cell array as recited in claim 26,wherein the ferroelectric capacitor has a surface area which is smallrelative to the surface area of the gate.
 28. The memory cell array asrecited in claim 26, wherein the ferroelectric capacitor comprises anedge defined ferroelectric capacitor.
 29. The memory cell array asrecited in claim 26, wherein data is written into the ferroelectriccapacitor when the wordline and source line are asserted and data isread from the non-volatile memory cell when the wordline, the digitlineand the source line are asserted.
 30. The memory cell array as recitedin claim 26, wherein an asserted source line comprises a grounded sourceline.
 31. The memory cell array as recited in claim 26, wherein thecharge amplifier amplifies the charge stored in the ferroelectriccapacitor by at least one order of magnitude.
 32. The memory cell arrayas recited in claim 26, wherein the charge amplifier amplifies thecharge stored in the ferroelectric capacitor by a predetermined gainfactor.
 33. The memory cell array as recited in claim 26, wherein thecharge amplifier comprises a transistor.
 34. The memory cell array asrecited in claim 33, wherein the transistor comprises a CMOS transistor.35. A processor based system, comprising: a processor; and a memory cellarray coupled to the processor, the memory cell array including aplurality) of memory cells organized as an array of rows and columns, atleast one of the memory cells being a non-volatile memory cellcomprising: a charge amplifier comprising a gate opposing a channelregion coupling source and drain regions; a digitline coupled to thedrain region; a source line coupled to the source region; an edgedefined ferroelectric capacitor coupled to the gate by a polysiliconinterconnect; a wordline coupled to the edge defined ferroelectriccapacitor; and a sense amplifier coupled to the digitline of the atleast one memory cell, wherein the edge defined ferroelectric capacitoris in a stacked alignment with an active gate oxide channel region ofthe charge amplifier.
 36. The processor based system as recited in claim35, wherein the charge amplifier comprises a transistor.
 37. Theprocessor based system as recited in claim 35, wherein, under thecontrol of the processor: data is written into the ferroelectriccapacitor when the wordline and the source line are both asserted; anddata is read out of the memory cell when the wordline, the digitline andthe source line are asserted.
 38. The processor based system as recitedin claim 35, wherein ferroelectric capacitor comprises an edge definedferroelectric capacitor.
 39. The processor based system as recited inclaim 35, wherein the ferroelectric capacitor comprises a dielectriclayer of lead zirconate titanate (PZT).
 40. The processor based systemas recited in claim 39, wherein the PZT comprising the ferroelectriccapacitor is of the form PbZr_(x)Ti_(1-x)O₃ with x ranging between 0.4and 0.53.
 41. A memory module, comprising: a substrate; a plurality ofmemory chips mounted on the substrate, wherein one or more of the memorychips comprise a memory cell array fabricated on a semiconductor chipand communicating with a processor, said memory cell array comprising atleast one non-volatile memory cell comprising an edge definedferroelectric capacitor operatively coupled to the gate of a chargeamplifier by a polysilicon interconnect, wherein the edge definedferroelectric capacitor is in a stacked alignment with an active gateoxide channel region of the charge amplifier.
 42. The memory module asrecited in claim 41, wherein: the junction formed at the gate has anintrinsic capacitance; and the capacitance of the ferroelectriccapacitor is based on the magnitude of the intrinsic capacitance. 43.The memory module as recited in claim 41, wherein: the junction formedat the gate has an intrinsic capacitance; and the physical size of theferroelectric capacitor is based on the magnitude of the intrinsiccapacitance.
 44. The memory module as recited in claim 41, wherein theferroelectric capacitor comprises a dielectric layer of lead zirconatetitanate (PZT).
 45. The memory module as recited in claim 18, whereinthe PZT comprising the ferroelectric capacitor is of the formPbZr_(x)Ti_(1-x)O₃ with x ranging between 0.4 and 0.53.
 46. The memorymodule as recited in claim 41, wherein the non-volatile memory cellcomprises: the charge amplifier, which comprises the gate disposedadjacent to a channel region coupling source and drain regions; adigitline coupled to drain region; a source line coupled to the sourceregion, the ferroelectric capacitor coupled to the gate; and a wordlinecoupled to the ferroelectric capacitor.
 47. A method for readinginformation from a one transistor/one capacitor (1T/1C) memory cellhaving a charge amplifier including a gate disposed adjacent to achannel region coupling source and drain regions, a digitline coupled tothe drain region, a source line coupled to the source region, an edgedefined ferroelectric capacitor coupled to the gate by a polysiliconinterconnect, and a wordline coupled to the ferroelectric capacitor,wherein the edge defined ferroelectric capacitor is in a stackedalignment with an active gate oxide channel region of the chargeamplifier, the method comprising: grounding the source line; assertingthe wordline and digitline; amplifying the charge on the edge definedferroelectric capacitor; and determining the resultant charge on thedigitline.
 48. The method as recited in claim 47, wherein the assertingstep further comprises asserting the wordline at a voltage less than thecoercive voltage of the ferroelectric capacitor.
 49. The method asrecited in claim 47, wherein the asserting step further comprisesasserting the digitline which has been charged to a predeterminedvoltage value.
 50. A method for writing information to a onetransistor/one capacitor (1T/1C) memory cell having a charge amplifierincluding a gate disposed adjacent to a channel region coupling sourceand drain regions, a digitline coupled to the drain region, a sourceline coupled to the source region, an edge defined ferroelectriccapacitor coupled to the gate by a polysilicon interconnect, and awordline coupled to the edge defined ferroelectric capacitor, whereinthe edge defined ferroelectric capacitor is in a stacked alignment withan active gate oxide channel region of the charge amplifier, the methodcomprising: asserting the source line; and asserting the wordline tothereby apply a potential greater than the coercive voltage of the edgedefined ferroelectric capacitor across the edge defined ferroelectriccapacitor and the charge amplifier.
 51. The method as recited in claim50, wherein the asserted source line comprises a grounded source line.52. A logic element, comprising: N+1 source/drain regions; N channels,each channel coupling adjacent ones of the N+1 source/drain regions; Ngates disposed adjacent to the N channels; N edge defined ferroelectriccapacitors, each of the N edge defined ferroelectric capacitors coupledto a respective one of the N gates by a polysilicon interconnect; adigitline coupled to an end one of the N+1 source/drain regions; and asource line coupled to the other end one of the N+1 source/drain regionswherein each of the N edge defined ferroelectric capacitors is in astacked alignment with an active gate oxide channel region of arespective one of the N gates.
 53. The logic element as recited in claim52, wherein the logic element is operated by assertion of all of the Ngates.
 54. The logic element as recited in claim 52, wherein theferroelectric capacitors comprise edge defined ferroelectric capacitors.55. The logic element as recited in claim 52, further comprising Nwordlines, each of the N wordlines coupled to a respective one of the Nferroelectric capacitors, wherein the logic element is operated byassertion of all of the N wordlines coupled to respective N gates.